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Built-in self-repair (BISR) techniques are widely used to enhance the yield of random access memories (RAMs) in a system-on-chip (SoC) which typically consists of hundreds of RAMs. Hence, many BISR circuits may be needed in a such SoC. Effective techniques for planning these BISR circuits thus are imperative. In this paper, we propose a memory BISR planning (MBiP) framework for the RAMs in SoCs. The...
This paper presents a reconfigurable built-in self-repair (ReBISR) scheme for multiple repairable RAM cores with different sizes and redundancy organizations (i.e., spare rows/spare columns or spare rows/spare IOs). We also propose an efficient built-in redundancy-analysis (BIRA) algorithm for allocating redundancies for the ReBISR scheme. A reconfigurable BIRA (ReBIRA) circuit is realized to perform...
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