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In this paper, we present a technique to remove the noise of a depth map while fill the missing regions of the depth map. Generally, the depth map is degraded during the sensing process, thermal noise, the condition of the atmosphere, and the occlusion by the objects. Different to the previous works which only adopt the joint image filters directly, we propose an automatic multi-resolution approach...
We present a Linear Feedback Shift Register (LFSR) like architecture, because the LFSR can bring a lot of data by using a few bits. We calculate the ATE data by Gauss-Elimination and put the ATE data to our decompression architecture to generate a lot of patterns. And one ATE data will run several times in the architecture. If some faults cannot be detected, we will generate the patterns which are...
A scheme that ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents an X-filling approach called adjacent backtracing fill (AB-fill). After AB-fill approach for at-speed scan testing, all of test patterns have assigned as partially-specified values with a small number of don't care bits (x) as in test...
This paper presents a test slice difference (TSD) technique to improve test data compression. It is an efficient method and only needs one scan cell. Consequently, hardware overhead is much lower than cyclical scan chains (CSR). As the complexity of VLSI continues to grow, excessive power supply noise has become seriously. We propose a new compression scheme which smooth down the switching activity...
In recent years, power dissipation is a large challenge for IC design. Furthermore, the capacitance excessive transition may lead to circuit reliable reduction and heat problem. In this paper, we proposed a new algorithm to reduce the transition count of scan cell during capture operation. The clock gating technique, fault diagnosis, and fault dropping are used to decrease the capture power dissipation...
This paper presents an input test data compaction and scan power reduction technique. We present new design for testability (DFT) method to hold values when some of test data in test cubes are not need to be changed. In our implementation, we present new algorithm called 2-D compaction to compact test cubes as less as possible and fill unspecified bits with specified value when necessary. Experimental...
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may use longer time and more power consumption in testing. In this paper, we propose a novel hardware architecture base on "LBIST Controller" to reduce test application time and test power consumption. Give a test cubes for stuck-at faults contain unspecified bit generated by a sequential...
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