The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents Adjacent Backtracing filling (AB-fillingl) which both adjacent and backtracing filling algorithms are used, is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT. After our approach for at-speed scan...
Generally speaking, the dependency data compression is very useful for Intellectual Property (IP) cores and SoC. We consider the shift-in power and compression ratio in low-cost ATE environment. We propose new compression architecture with fixed length for running ones. We suppose that the ATE has not repeated function and synchronization signal. In the results, when the complexity of VLSI circuit...
We present a Linear Feedback Shift Register (LFSR) like architecture, because the LFSR can bring a lot of data by using a few bits. We calculate the ATE data by Gauss-Elimination and put the ATE data to our decompression architecture to generate a lot of patterns. And one ATE data will run several times in the architecture. If some faults cannot be detected, we will generate the patterns which are...
In recent years, power dissipation is a large challenge for IC design. Furthermore, the capacitance excessive transition may lead to circuit reliable reduction and heat problem. In this paper, we proposed a new algorithm to reduce the transition count of scan cell during capture operation. The clock gating technique, fault diagnosis, and fault dropping are used to decrease the capture power dissipation...
This paper presents an input test data compaction and scan power reduction technique. We present new design for testability (DFT) method to hold values when some of test data in test cubes are not need to be changed. In our implementation, we present new algorithm called 2-D compaction to compact test cubes as less as possible and fill unspecified bits with specified value when necessary. Experimental...
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may use longer time and more power consumption in testing. In this paper, we propose a novel hardware architecture base on "LBIST Controller" to reduce test application time and test power consumption. Give a test cubes for stuck-at faults contain unspecified bit generated by a sequential...
Test access mechanism (TAM) and testing schedule for system-on-chip (SOC) are challenging problems. Testing schedule must be effective to minimize testing time, under the constraint of test resources. This paper presents a new method based on generalized rectangle packing, as two-dimensional packing. A core cuts into many pieces and utilizes the design of reconfigurable core wrappers, and is dynamic...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.