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Distributed cache is capable of accelerating the process of retrieving an enormous amount of data. In order to optimize the cache performance in distributed environment, we present an architecture of cache replacement algorithms. The architecture called HQ (Hybrid Queue) focuses on organizing distributed cache clusters hierarchically, making use of the web data distribution. In addition, we also introduce...
As FPGA architecture evolves, complex heterogenous blocks, such as RAMs and DSPs, are widely used to effectively implement various circuit applications. These complex blocks often consist of datapath-intensive circuits, which are not adequately addressed in existing packing and placement algorithms. Besides, scalability has become a first-order metric for modern FPGA design, mainly due to the dramatically...
Compared with the traditional two-dimensional (2D) deployment form, three-dimensional (3D) deployment of sensor network has greater research significance and practical potential to satisfy the detecting needs of targets with complex properties. In this paper, a method for 3D deployment optimization of sensor network based on an improved Particle Swarm Optimization (PSO) algorithm is proposed. Many...
Packet classification is an important topic for high speed routers nowadays. There are many packet classification algorithms based on decision tree like Hicuts, Hyper cuts and Hyper split. Because Hicuts and Hyper cuts divides the rule sets by cutting the address space into equal-sized subspaces, their cutting efficiency is not good. Although Hyper split proposed a good end-point-based cutting scheme,...
Due to the limitation of computing complexity, it is difficult to apply the H.264 deblocking filter to low-end terminals. Although some technologies to optimize it have been proposed, the complexity is still high for real time implementation. Considering that deblocking filter is applied to all of the vertical and horizontal edges of 4times4 blocks but only some of them actually need to be filtered...
In this paper, we propose a constraint graph-based macro placement algorithm that removes macro overlaps and optimizes macro positions for modern mixed-size circuit designs. Improving over the constraint graph by working only on its essential edges without loss of the solution quality, our algorithm can search for high-quality macro placement solutions effectively and efficiently. Instead of packing...
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