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A three-layer-stacked wafer with CMOS devices was fabricated for the first time by using hybrid wafer bonding and backside-via-last TSV (7-μm diameter/25-μm length) processes. Successful fabrication of this wafer confirmed that copper/polymer hybrid wafer bonding brings both seamless copper bonding and void-less underfilling in face-to-face (F2F) and back-to-face (B2F) configurations. The backside-via-last...
Wafer-level hybrid copper/polymer bonding technology suitable for wafer-level 3D integration (called “thinning after bonding”) was developed. A damascene process is applied for fabricating copper pads. After chemical mechanical polishing (CMP), a globally flat bonding surface is obtained by co-planarization of copper and polymer during barrier CMP. The key to this co-planarization process is optimizing...
To establish the method for evaluating interconnect LER, resist, low-k, and Cu/low-k samples were observed and electric-field enhancement was simulated. Wedge-shape LER was observed in the edges of low-k and Cu/low-k patterns, and simulations showed that the wedge causes serious electric-field enhancement which can degrade TDDB property. To predict the risk of TDDB, inspections of the wedge angle...
The impact of backside Cu contamination during the 3D integration process was investigated and found that Cu diffusion was significantly enhanced by stress relief and wafer thinning. The thermal scattering phenomenon of Cu is inevitable even under a low-temperature assembly process, which also caused Cu contamination. To prevent the Cu contamination, an Ar ion implantation for Cu gettering and a SiN...
We have developed a new Cu-barrier dielectric film suitable for Cu/low-k integration. The film has an SiO/sub 2/ composition and is deposited using trimethoxysilane and N/sub 2/O chemistry. The Cu barrier properties of the film are as good as those of the conventional barrier material (P-SiN). The dielectric constant (k) of the film is 3.9, which is about half the dielectric constant of P-SiN film...
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