The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, an efficient method to relax timing requirements of CRFF sigma-delta modulators has been proposed. A system optimization to circuit level design was finished. Class-C inverter was used to realize half delay integrators of the proposed structure. A 4th-order 1-bit CRFF topology was implemented in smic 0.13μm CMOS technology. With 31.25MHz sampling frequency and 64x oversampling ratio,...
Using an auxiliary quantizer before unity-STF SDM, a novel 3rd-order dual-quantizer SDM with extended dynamic range is presented. With hybrid distributed feedback & feedforward paths and an internal feedforward path, a novel low-distortion 3rd-order SDM with simple adder before quantizer is proposed as the unity-STF SDM. Simulations show their perfect immunity to non-idealities.
In this paper, a novel design method has been proposed to realize feed-forward low-distortion unity STF sigma-delta modulators which are the critical blocks in multi-loop SMASH structure. Using the method, a timing-relaxed stable unity STF 2nd-order modulator has been proposed in detail. After that, an extremely high-resolution SMASH 2(3b)-2(3b)-1(2b) has been suggested using the proposed stages....
In this paper, two high-resolution medium-bandwidth single-loop 4th-order single-bit sigma-delta modulators using a feed-forward and a feedback topology respectively are implemented in 0.13μm CMOS technology. The oversampling ratio is 50 with 312.5kHz input bandwidth, 14.66-bit and 16.62-bit resolution have been reached. The two circuits each consume about 8-mW from a single 1.2V supply voltage. After...
In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been proposed in this paper. First, a MASH 2-2 with feed-forward topology in both stages has been explained to obtain low-distortion property and remove subtraction Second, a flexible SMASH 2-2...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.