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In this paper we present a design of adaptive gain phase-locked loop (PLL) which features fast acquisition, low jitter and wide tuning range. A dual-edge-triggered phase frequency detector (PFD) and a self-regulated voltage controlled oscillator (VCO) are employed in this design to realize the aforementioned properties. The measured results show that the experimental chip with a standard logic 0.5-mum...
A 6-bit 250MHz low-power CMOS fully-folding analog-to-digital converter is designed in a 0.5mum standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one. A novel bit synchronization architecture also based on folding circuits is presented to reduce the number of comparators for bit synchronization and simplify the logic design. The total power dissipation...
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