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The end of Dennard's scaling poses computer systems, especially the datacenters, in front of both power and utilization walls. One possible solution to combat the power and utilization walls is dark silicon where transistors are under-utilized in the chip, but this will result in a diminishing performance. Another solution is Near-Threshold Voltage Computing (NTC) which operates transistors in the...
Investigating that some face regions are possibly more reliable than the others when verifying two face images due to the local abnormal differences caused by the uncontrolled factors in unconstrain environment,we propose a novel face verification algorithm based on pairwise pre-estimation. In our algorithm, we estimate the reliability of a face region by detecting abnormal differences on some key...
Phased-Mission System (PMS) is a kind of typical complex systems. Most weapon systems executing battle mission and usage mission belongs to this type of complex systems. PMS and its' mission sustainability evaluation parameters included mission reliability, dependability, and mission effectiveness are given. In view of the usage characteristics of fact weapon system, some hypotheses are given for...
To ensure sustainable operations of wireless sensor networks, environmental energy harvesting has been well recognized as one promising solution for long-term applications. Unlike in battery-powered sensor networks, we are targeting a duty-cycle adjustment to optimize the network performance, e.g., delay minimization, with full harvested energy utilization. In this paper, we introduce a set of duty-cycle...
Naval ship formation is one of the main counterwork forms in modern sea battles. Reliability theory is used to study naval ship formation deployment. First, a measure method for the cooperative quality of the shipborne equipments in the formation is given based on the concept of reliability degree. Then an optimized deployment of naval fleet is established with consideration of the cooperative quality...
The general-purpose computation on graphic processing units (GPGPU) becomes increasingly popular due to their high computational throughput for data parallel applications. Modern GPU architectures have limited capability for error detection and tolerance since they are originally designed for graphics processing. However, the rigorous execution correctness is required for general-purpose applications...
Fracture failure is one of the main failure modes of Micro-electromechanical system (MEMS). Based on studying MEMS's fracture failure mechanism, the reliability models for MEMS fracture failure under mechanical stress field, electrostatic field, and alternating electric field are built with mechanical reliability methods. The model building process is shown by an application case. These models supply...
Phase change memory (PCM) is emerging as a promising solution for future memory systems and disk caches. As a type of resistive memory, PCM relies on the electrical resistance of Ge2Sb2Te5 (GST) to represent stored information. With the adoption of multi-level programming PCM devices, unwanted resistance drift is becoming an increasing reliability concern in future high-density, multi-level cell PCM...
With more and more data created by grid computing, large file distribution is a key issue in data grid. Current file distribution in data grid is usually a style site-to-site and this mechanism is not efficient and wastes bandwidth. In this paper, we propose a novel algorithm to distribute large file efficiently in data grid. We split the file into n subfiles and transfer each subfile to a different...
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior studies have shown that chip operating frequency and leakage power can have large variations due to fluctuations in transistor gate length and sub-threshold voltage. In this work, we study the impact of process variation on...
As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance microprocessors fabricated using state-of-the-art CMOS technologies. Emerging 3D chip integration techniques leverage vertically stacked structures to reduce on-chip wire delay and have shown the capability of overcoming interconnect...
Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Parametric variation introduced by nano-scale device fabrication inaccuracy can exacerbate the PMOS transistor wear-out problem and further reduce the reliable lifetime of microprocessors. In this work, we propose microarchitecture...
High performance and reliability are essential for microprocessor design. As semiconductor processing technology continues to move toward smaller and denser transistors, lower threshold voltages and tighter noise margins, microprocessors are becoming more susceptible to transient faults (soft errors) that can affect reliability. The increasing chip soft error rates make it is necessary to estimate...
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) processors. However, exploiting more parallelism yields high susceptibility to transient faults on a conventional IQ. With the rapidly increasing soft error rates, the IQ is likely to be a reliability hot-spot on SMT processors...
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transient faults, also known as soft errors, corrupt program data at the circuit level and cause incorrect program execution and system crashes. Future processors will consist of billions of transistors organized as multicore microarchitectures...
In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent total leakage power of a large circuit block, considering Ijunc, sub-threshold leakage (Isub), and gate oxide leakage (Igate). We then propose our algorithm to estimate the full-chip leakage power with consideration of both...
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