The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Strain techniques have been adopted and widely used in the advanced nodes since early 65nm for carrier mobility improvement. For PMOS, eSiGe incorporation in the SD is the process of choice to induce compressive strain in the channel for mobility improvement. To further lower the contact resistance, it is preferred to boost Boron concentration for pSD formed by eSiGe process. Normal implant process...
In this letter, for the first time, the integration benefits of a molecular carborane (CBH-C2B10H12) implant on a state-of-the-art 28-nm logic flow are demonstrated and discussed via advanced modeling. It is shown that, by integrating CBH, pLDD formation can be optimized to provide device benefits via profile/damage engineering.
We investigated molecular carbon (C16H10) implant as a replacement for both a monomer carbon co-implant as well as a Ge pre-amorphization step for ultra-shallow junction (USJ) formation in a p-MOSFET SDE doping process in a 40 nm logic device. Carbon is often used in the p-FET extension sequence because it reduces transient enhanced diffusion (TED) by trapping silicon interstitials. However, a Ge...
In NAND flash, devices are normally erased to negative Vt and then programmed to positive Vt. In this work we introduce a novel depletion-mode (normally on) buried-channel, junction-free n-channel NAND flash device. The buried-channel NAND flash shifts the P/E Vt ranges below those for the conventional surface-channel device, and is more suitable for the NAND Flash memory design. Due to the lower...
We have successfully demonstrated a novel junction-free BE-SONOS NAND Flash. Junction-free devices greatly improve the short channel effect and thus promise scaling of NAND Flash below 20 nm node. Instead of S/D junctions a very small space (Lt 30 nm) is left between adjacent devices. Junction is formed only at the outer region of NAND array, while there is no junction inside the array. Fringe field...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.