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This paper proposes HSTL based energy efficient design of frame buffer for a digital image processor. Our aim is to make energy efficient frame buffer design and for that reason we are using different types of HSTL IO standards. This design is implemented on both Virtex-6 FPGA and Airtex-7 FPGA and compared the power dissipation. It is observed that at 1GHz operating frequency, there is maximum IO...
The high leakage current has been one of the critical issues in SRAM-based Field Programmable Gate Arrays (FPGAs). In recent works, resistive non-volatile memories (NVMs) have been utilized to tackle the issue with their superior energy efficiency and fast power-on speed. Phase Change Memory (PCM) is one of the most promising resistive NVMs with the advantages of low cost, high density and high resistance...
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