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A low power and full ASIC MPEG-2/4 AAC single chip decoder is presented. The decoding blocks are partitioned into four dedicated hardware modules with the complexity and operational type analysis. Through algorithm, architecture, RTL and circuit level lower power techniques, the proposed AAC decoder is operated at 1.4 MHz for the 44.1 KHz sampling frequency and consumes only 0.21 mW using TSMC 0.13...
In complex SoC design, the reusable IP is very useful to achieve the whole system with high verification. Based on this issue, a hardware and software (HW/SW) co-design approach can obtain maximum performance, and is easily integrated with the other functions to complete the system. This paper presents the multi-standard audio decoder design with hardware/software co-design flow. First we need to...
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