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A serial-link repeater chip with a single stage continuous-time linear equalizer (CTLE) and a 3-tap feedforward equalizer (FFE) is realized in a 0.13μm SiGe BiCMOS technology. The CTLE with the negative capacitance circuits is implemented to achieve a larger high-frequency boosting at the receiver side. By utilizing the LC-based delay elements, the FFE accomplishes the transmitter de-emphasis without...
This paper describes the design of a wireline repeater in 65nm CMOS technology. The T-coil networks with ESD protection are used in both repeater's input and output to realize impendence matching and bandwidth enhancement. Three continuous time linear equalizers (CTLE) placed in the data path are used to compensate for high frequencies loss, while the current mode logic (CML) buffer chain is used...
In this paper, a 3–10 Gbps source synchronous receiver macro in 65 nm CMOS technology is presented. The receiver consists of 5 data lanes and a forwarded clock lane, featuring a wide frequency operating range. In the forwarded clock lane, a duty cycle correction loop is implemented to cancel the clock duty cycle distortion. A DLL with a wide locking range from 1 to 6 GHz is designed to generate quadrature...
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