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To capture detailed routing congestion factors in sub-90nm technology nodes, we propose a practical congestion model embedded in 3-D global routing grid graph. Using a concept of pass-through capacity and demand, intra-gcell congestion contributed by fat vias, stacked vias, local nets and related design rules can be measured and optimized. Proposed congestion model is compatible with existing widely-used...
For faster timing closure, a parasitic extraction method is developed for the pre-route VLSI design. This method generates virtual route and estimates congestion using the placement information of standard cells, and then extract the interconnect parasitics with the pattern-library method. The techniques of generating parasitic RC tree according to the improved FLUTE algorithm, and capacitance extraction...
In this paper we propose an improved approach for mixed-size detailed placement. First, we legalize macros with the using of constraint graph. Then, we remove overlaps between macros and standard cells, even the placement region and reduce the wirelength by moving the standard cells, and a dynamic programming method is used to legalize the standard cells. Finally, we further reduce the wirelength...
As VLSI technology scales into sub-65 nm realm, the complexity of timing optimization is drastically increased by the consideration of power and variations. Even though designers make great efforts during physical design, they are often faced with still heavy timing violations in deep post-routing stages. For the entire design convergence and timing closure, especially under current multi-corner multi-mode...
In this paper we present a multilevel hypergraph partitioning algorithm which satisfies not only vertex weight constraint but also edge weight constraint. In our multilevel paradigm, two FM (Fiduccia and Mattheyses, 1988) variants are performed alternately in the refinement stage. The first FM variant aims to symmetrize edge weight of the two partitioning blocks and the other aims to minimize cut...
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