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This work describes a CMOS dual-modulus prescaler using double-edge-triggered (DET) D-flip-flops. This technique enables a frequency synthesizer to be divided by 64/64.5. Simulation results show that 35% reduction of power dissipation can be obtained. Using a 0.25mum process, a dual-modulus prescaler can operate at 1.8GHz while dissipating 5.525 mW power
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