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A 5th-order switched-capacitor (SC) complex filter is implemented in 0.2-??m CMOS technology. In order to reduce the die size and current consumption of the complex filter, a novel SC integrator is developed. The filter is centered at 24.8 kHz with bandwidth of 20.2 kHz. The Image channel is attenuated by more than 40 dB. The in-band 3rd order harmonic input intercept point (IIP3) is 15 dBm and the...
A new phase-backed loop (PLL) with a simple architecture that overcomes the trade-off problem between acquisition time and phase noise was fabricated in a 0.2 mum CMOS process. One-fifth of the acquisition time of the integer-JV is achieved by switching only the division ratio with the optimised damping factor to control the natural frequency.
A micro-power active-RFID LSI with an all-digital RF-transmitting scheme achieves experimental 10-m-distance communication with a 1-Mbps data rate in the 300-MHz frequency band. The IC consists of a RF transmitter and a power-supply circuit, which controls the energy flow from the battery to the IC, and offers intermittent operation of the RF transmitter. The IC draws 1.6 μA from a 3.4-V supply and...
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