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In this paper we describe a 90 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. We compare TLP results of SOI MOSFETs and diodes to bulk devices. We present a new response surface method to optimize device sizes in the ESD networks and show circuit level data comparing TLP test results and SPICE simulation results of an I/O test circuit...
A new, area efficient, boosted and distributed active MOSFET rail clamp network for I/O pad ESD protection is presented. In addition, a compact new rail clamp trigger circuit with high resistance to false triggering is introduced.
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