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In this paper we describe a 90 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. We compare TLP results of SOI MOSFETs and diodes to bulk devices. We present a new response surface method to optimize device sizes in the ESD networks and show circuit level data comparing TLP test results and SPICE simulation results of an I/O test circuit...
In this paper we propose new circuit design options for increasing the ldquoeffectiverdquo failure voltage (Vt2) of both NMOS and PMOS output buffer transistors, thereby helping to protect these fragile devices. Using experimental data, device and circuit simulations we demonstrate how placing a series resistor and either a bias circuit for the buffer gates or secondary ESD diodes may significantly...
We present a new boosted and distributed ESD rail clamp protection approach for high voltage CMOS applications using stacked active MOSFET rail clamps and provide design guidelines for practical pad ring scenarios. This approach offers improved ESD robustness, area compactness, layout modularity, process portability, scalability, and ease of simulation.
A new, area efficient, boosted and distributed active MOSFET rail clamp network for I/O pad ESD protection is presented. In addition, a compact new rail clamp trigger circuit with high resistance to false triggering is introduced.
This paper introduces a new distributed active MOSFET rail clamp network that offers surprising advantages in layout area efficiency, bus resistance tolerance, design modularity and ease of reuse. SPICE simulation results using an extended vertical PNP bipolar transistor compact model and a new method for optimizing distributed rail clamp networks are presented along with chip-level test results.
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