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The Pulsar IIb is a general purpose FPGA-based processor board designed for full mesh ATCA backplanes. This hardware was originally designed to support Level-1 silicon track trigger R&D projects at the LHC. Each ATCA carrier board is required to support the Intelligent Platform Management Interface (IPMI) protocol, which is responsible for coordinating hot swap operations and for exchanging sensor...
As the LHC luminosity is ramped up to 3×1034 cm-2 s-1 and beyond, the high rates, multiplicities, and energies of particles seen by the detectors will pose a unique challenge. Only a tiny fraction of the produced collisions can be stored on tape and immense real-time data reduction is needed. An effective trigger system must maintain high trigger efficiencies for the physics we are most interested...
The silicon-vertex-trigger (SVT) [1,2] at CDF is made of two pipelined processors: the associative-memory, AM [3,4], finding low precision tracks (roads) and the track-fitter, TF, refining the track quality with high-precision fits. We propose to extend the SVT use, now mostly focused on B-physics, to high-PT physics as a tracker in the forward/backward region. The upgraded SVT structure is easily...
This paper presents a new approach to detecting faults in interconnects; the novelty of the proposed approach is that test generation and scheduling are established using the physical characteristics of the layout of the interconnect under test. This includes critical area extraction and a realistic fault model for a structural methodology. Physical layout information is used to model the adjacencies...
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