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This paper systematically analyzed the tradeoff between writing operation time and tail bit of LRS, and provided the optimal writing operation time for 1T1R RRAM with the target LRS 500kn and HRS 10Mn. Under three different cases of pulse width, the experiment results all show that the optimal voltage amplitude and step could achieve a good tradeoff between writing operation time and tail bits of...
A 16Mb RRAM Chip with source line (SL) current limitation and a novel programming strategy is developed. Comparing with traditional gate control current method, SET operation with source current control can significantly narrow the read current distribution. The programming strategy is optimized simultaneously using a low current multi-step forming and single pulse program operation. With these optimizations,...
This paper systematically analyzed and optimized the operation parameters of low current 1T1R RRAM arrays. Considering both thermal and electrical field driven effects, a current and voltage joint verification strategy has been proposed. Highly uniform multilevel resistive switching performances with LRS resistance higher than 100kΩ and HRS resistance higher than 10MΩ were obtained on 130nm CMOS process...
In this letter, TiN/TaO$_{\mathrm {\mathbf {y}}}$ /Ta2O5–x/Pt-based resistive switching devices were fabricated and tested. Short time high-resistance state instability phenomenon was observed during pulse programming verification measurement. This instability phenomenon was observed in about a minute after the RESET operation for high resistance states. In contrast, the measured low-resistance states...
Memristor is a promising device in neuromorphic computing application by working as the basic element in the synapses array. To overcome the disadvantage (e.g. sneak path) and inconvenience (e.g. programming operation) of the 2-terminal 1R or 1S1R based RRAM cross-bar, we propose a new hardware structure and appropriate operation to implement a one transistor one resistor (1T1R) array. By MATLAB and...
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