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This paper focuses on compact and configurable multiple-valued (MV) encoders. For this purpose, a new cyclic D/A converter circuit using semi floating-gate (SFG) inverters is proposed. Slow conversion rates are considered a problem in cyclic D/A converters. A new algorithm called Dual Data Rate (DDR) mode of operation is introduced allowing two iterations per clock cycle instead of only one when using...
This paper introduces a structure for self-refreshing multiple valued memory. The idea is to use structures having repeating patterns, to represent different saved values. Assuming a clocked repeating finite pattern, each pattern will repeat themselves after a finite number of clock pulses N, having N different phases. The values saved will be represented by both a pattern, and the phase of the pattern...
This paper introduces a multiple valued counter, based on recharged semi floating gate structures. The counter starts at a sampled voltage, and counts from there, using an input clock signal as an input. Depending on the sampled value and the phase of the input clock signal - the counter can count both up and down. The counting steps can be varied adjusting the input clock amplitude, which in combination...
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