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A time-interleaved 12-b SAR ADC, employing the proposed digital calibration with a delay-sampling technique to correct timing skew, achieves a 600-MHz sampling rate. The 600-Ms/s ADC has been fabricated in a 40-nm CMOS technology, improving SFDR from 55 dB to 71 dB for a 100-MHz input signal. The 4-way interleaved ADC achieves a 61-dB SNDR while dissipating 23 mW from a 0.9-V power supply.
The impact on performance of Nyquist-rate analog-to-digital converters (ADC) with the presence of sampling clock jitter is first reviewed. Then the sampling clock jitter requirement is investigated based on the linearly approximated sampling model as well as the generic autocorrelation function approach. This leads to the motivation for cancelling the jitter-induced error in the digital domain. Two...
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