The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, we present a new compact, high-input-impedance amplifier for neural signal acquisition. In this design, current feedback is achieved in a modified fully differential folded cascode amplifier to isolate the input signal from the feedback connection and thus increase the input impedance of the preamplifier. Common mode feedback circuits and ponderous capacitors are eliminated by using...
In this testing paper, the computer-based method for analysing power flow and fault studies will be introduced. Specifically, a commercial power system analysis package IPSA+ will be introduced and used in this test. The objective of this testing report is to introduce the fundamentals of IPSA+ and the analytical methods of power flow and fault using IPSA+. Specifically, we design a five-step testing...
The Electro Static Discharge (ESD) test is required for all electronic products today. The conventional ESD protection approach is based on two reverse-biased diodes. However, for the high frequency system such as the millimeter wave communication transceivers, the conventional ESD protection circuit “kills” the performance due to the parasitic capacitance of the diodes under high frequency. This...
Differential interconnect lines in multi-gigabits system in package (SiP) packaging system are studied in this paper. The performance of interconnect lines can be easily estimated with jitter and eye opening using the eye diagram that is very helpful metric. To maintain good eye-diagram with high voltage swing and low timing jitter, a signal integrity (SI) design flow of SiP is proposed based on eye-diagram...
This paper presents an electrical design of a 6.25Gbps×12-channel parallel optical transceiver with SiP packaging technology. Considering such high speed, a low impedance and low noise power distribution network (PDN) is designed to suppress simultaneous switching noise (SSN) and a novel embedded capacitor filter is used to replace the conventional power supply filter. To minimize the impedance discontinuity...
This paper presents a design of an optical transceiver SiP with an embedded capacitor which replace conventional filter network and suppress switching noise with a large bandwidth in multi-GHz PCBs. A SI design method was proposed based on electromagnetic analysis method and circuit analysis method. To study SI, a SPICE equivalent circuit model of the high speed I/O link was built based on transmission...
Extracellular neural recording requires neural probes having more recording sites as well as limited volumes. With its mechanical characteristic and abundant process method, Silicon is a kind of material fit for producing neural probe. Silicon on insulator (SOI) is adopted in this paper to fabricate neural probes. The uniformity and manufacturability are improved. The fabricating process and testing...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.