The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A 1.5–2.5 GHz current-mode logic (CML) ring oscillator-based supply-insensitive phase-locked loop (PLL) employing two different topologies of CML ring oscillators that compensate for the supply variations is presented. In addition, an on-chip calibration scheme is designed to ensure the voltage-controlled oscillators (VCOs) to operate at the optimum operating point where the PLL achieves nearly the...
To research performance verify of the high speed centrifugal compressor between the two different conditions with the different circumferential grooves and with untreated smooth wall, the 3-dimentional numerical simulations were performed in a high speed centrifugal compressor with the 8 different circumferential grooves casing treatment. Detailed analyses of the flow visualization at the tip of blades...
The casing treatments have the potential to extent the operating range of centrifugal compressor. To research performance verify of the high speed centrifugal compressor between the different conditions with the different casing treatments and with untreated smooth wall. The time accurate 3-dimentional numerical simulations are performed in a high speed centrifugal compressor with the different casing...
We introduce a ??bulk data transfer?? (BDT) mechanism across multi-autonomous system (AS). The mechanism performance is limited by the positions of source or replica servers and by the inter/intra AS routing strategies. Therefore, a new mechanism is proposed to enable the source peer to create several virtual replica servers to transfer the data to the destination peer together. The mechanism works...
This paper presents ISCLEs, a novel and robust analog design method that promises to scale with Moorepsilas Law, by doing boosting-style importance sampling on digital-sized circuits to achieve the target analog behavior. ISCLEs consists of: (1) a boosting algorithm developed specifically for circuit assembly; (2) an ISCLEs-specific library of possible digital-sized circuit blocks; and (3) a recently-developed...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.