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This paper reports a comprehensive electrostatic discharge (ESD) protection circuit co-design and analysis approach for high-frequency and high-speed ICs. Implemented in a 28nm CMOS, the ESD co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, parasitic ESD parameter extraction and ESD circuit evaluation for up to 40Gbps I/O circuits. This practical ESD co-design...
We report the first fuse-based field-dispensable electrostatic discharging (ESD) protection structure to eliminate the ESD-induced parasitics, hence, enable ultrahigh-speed ICs with robust ESD protection. Silicon results validate the new ESD protection concept for more than 20 Gb/s ICs in a 28-nm CMOS.
Design of single-pole multiple-throw (SPMT) Tx/Rx switch for RF FEM for multi-mode multi-frequency smartphones is challenging. SPMTs in SOI CMOS show comparable specs to those in GaAs due to unique SOI properties [1-3]. Hand-held devices require high ESD protection with more parasitic capacitance (CESD) that can severely degrade RF IC specs [4-6]. We recently designed the first highly-linearity SP10T...
This paper reports the first 8kV+ ESD-protected SP10T transmit/receive (T/R) antenna switch for quad-band (0.85/0.9/1.8/1.9-GHz) GSM and multiple W-CDMA smartphones fabricated in an 180-nm SOI CMOS. A novel physics-based switch-ESD co-design methodology is applied to ensure full-chip optimization for a SP10T test chip and its ESD protection circuit simultaneously.
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