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Ternary logic has inherently the potential of high computational speed in comparison with conventional binary logic. A new low-transistor-count, high-speed ternary half adder is presented in this paper. Carbon nanotube field effect transistors are utilized to realize the new design methodology. Unique characteristics of this technology provide multi-Vt circuitry with the flexibility which is highly...
Full adder is among the most practical logic blocks. It is the main arithmetical component of all digital systems. This paper presents the novel design of a high-speed and high-efficient full adder cell which is on the basis of low-complex passtransistor logic. Using carbon nanotube field effect transistors, formation of transmission gates are not required and the usage of extra transistors is avoided...
In this paper a new high-speed and high-performance Full Adder cell, which is implemented based on CMOS bridge style and minority function, is proposed. Several simulations conducted at nanoscale using different power supplies, load capacitors, frequencies and temperatures demonstrate the superiority of the proposed design in terms of delay and power-delay product (PDP) compared to the other cells...
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