The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, a supply current test method of 3D ICs is proposed to detect open defects occurring at interconnects between two dies in which IEEE 1149.1 architecture is implemented and locate the defective interconnects. Also, a testable design method is proposed for the test method and a testable designed IC is prototyped. Furthermore, testability of the test method is evaluated by some experiments...
It is believed that resistive open faults can cause small delay defects at wires, contacts, and/or vias of a circuit. However, it remains to be elucidated whether any methods could diagnose resistive open faults. We propose a method for diagnosing resistive open faults by using a diagnostic delay fault simulation with the minimum detectable delay fault size. We also introduce a fault excitation function...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.