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Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1–4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM...
This paper studies the TSV-to-TSV coupling issues in 3D ICs and introduces a methodology for performing signal integrity (SI) analysis considering TSV-to-TSV coupling for 3D ICs. 3D SI analysis results show that TSV coupling has big impact on the SI in 3D ICs. A TSV-KOZ sizing methodology and a force-directed placement-refinement approach are proposed to alleviate the 3D SI problem. Experimental results...
It is widely-known that coupling exists between adjacent through-silicon vias (TSVs) in 3D ICs. Since this TSV-to-TSV coupling is not negligible, it is highly likely that TSV-to-TSV coupling affects crosstalk significantly. Although a few works have already analyzed coupling in 3D ICs, they used S-parameter-based methods under the assumption that all ports in their simulation structures are under...
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significant coupling noise and timing problems despite that TSV count is much smaller com- pared with the gate count. Two approaches are proposed to alleviate TSV-to-TSV coupling, namely TSV shielding and buffer insertion. Analysis results...
In this paper we present a test structure and design methodology for testing, characterization, and self-repair of TSVs in 3D ICs. The proposed structure can detect the signal degradation through TSVs due to resistive shorts and variations in TSV. For TSVs with moderate signal degradations, the proposed structure reconfigures itself as signal recovery circuit to improve signal fidelity. The paper...
In this paper, we study the signal integrity issues of through-silicon-via (TSV)-based 3D IC layouts. Unlike the most existing work, our study reports the coupling noise among all nets and all TSVs used in a real processor design implemented in 3D. Our RTL-to-GDSII design flow consists of commercial tools, enhanced with various add-ons to handle TSV and 3D stacking. Using this tool flow, we generate...
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