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In this paper, a Nios II processor based hardware/software co-design architecture with high expandability and development flexibility is proposed. The architecture integrates a pipelined color space converter (CSC), hardware accelerator (HA), and a LCD touch module (LTM) HA, which facilitates a high-speed implementation of RGB to YCbCr color space conversion with a real-time image display. To avoid...
This paper proposed a speed controller design for a DC motor by using a FPGA chip and applies it on a wheeled robot. For the motor accelerating control, this paper proposed a hardware PI controller circuit module to achieve the accelerating control. On the motor decelerating control, this paper proposed a braked deceleration circuit module to improve the skid of tires when the wheel-type robot brakes...
In this paper, a Hardware/Software (HW/SW) co-design method of ant colony optimization (ACO) algorithm is proposed to implement on the FPGA chip. In this paper, the software is designed with C language and hardware is designed with Verilog hardware description language (HDL). The HW/SW co-design method is a technique based on a SOPC (System on a Programmable Chip). In this paper, the path selecting...
A servo motor controller design for robotic manipulator is proposed in this paper. This servo motor controller is used to control a manipulator, which has servo motors EX-106, to accomplish the movement of gripping some goods. This servo motor controller consists of three modules: (1) SOPC System Module, (2) Command Transform Module, and (3) Motor Control Module. This servo motor controller architecture...
This paper presents a hardware/software co-design method for particle filter based on System On Program Chip (SOPC) technique. Considering both the execution speed and design flexibility, we use a NIOS II processor to calculate weight for each particle and a hardware accelerator to update particles. As a result, execution efficiency of the proposed hardware/software co-design method of particle filter...
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