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Power density has become the major constraint for many on-chip designs. As an introduction to the Special Issue on Dark Silicon, the authors provide the newest trends and a survey on the topic that has valuable information for novices and experts alike.
Many-core processors exhibit hundreds to thousands of cores, which can execute lots of multi-threaded tasks in parallel. Restrictive power dissipation capacity of a many-core prevents all its executing tasks from operating at their peak performance together. Furthermore, the ability of a task to exploit part of the power budget allocated to it depends upon its current execution phase. This mandates...
Ability to supply more transistors per chip is outpacing improvements in cooling and power delivery. The result is operation that selectively powers on or off subsets of transistors. This paper suggests innovate ways to take advantage of the consequent “dark” silicon to meet a pair of additional emerging challenges—reliability and tolerance of variability.
Run-time mixed-grained reconfigurable architectures emerged as an efficient solution to deal with the heterogeneous and at-design-time unpredictable nature of advanced applications. Due to interconnection limitations, the reconfigurable elements are grouped into tiles communicating through an on-chip network. State-of-the-art run-time accelerator binding schemes, i.e., mapping the accelerators to...
Dark Silicon refers to the observation that in future technology nodes, it may only be possible to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache blocks and so on) in order to stay within the power budget and safe thermal limits, while the other resources will have to be kept powered-off or “dark”. In other words, chips will have an abundance of transistors,...
This paper describes an approach that allows using the potential of reconfigurable processors in an efficient and adaptive manner. Some architectural design decisions (e.g., the provided memory interface, number of ports, and bit-width per port) have a strong impact on the efficiency, whereas other design decisions (e.g., how the reconfigurable fabric is used to implement application-specific accelerators)...
Pipelined MPSoCs provide a high throughput implementation platform for multimedia applications, with reduced design time and improved flexibility. Typically a pipelined MPSoC is balanced at design-time using worst-case parameters. Where there is a widely varying workload, such designs consume exorbitant amount of power. In this paper, we propose a novel adaptive pipelined MPSoC architecture that adapts...
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