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High throughput demands have resulted in enormous increase in complexity of multicast video applications, which require multiple video encoders to simultaneously compress individual views. In this paper, we present an approach to encode independent videos using H.264 intra encoder on a single hardware platform, where the hardware resources are shared by independent encoders in a time-multiplexed manner...
Run-time mixed-grained reconfigurable architectures emerged as an efficient solution to deal with the heterogeneous and at-design-time unpredictable nature of advanced applications. Due to interconnection limitations, the reconfigurable elements are grouped into tiles communicating through an on-chip network. State-of-the-art run-time accelerator binding schemes, i.e., mapping the accelerators to...
This paper describes an approach that allows using the potential of reconfigurable processors in an efficient and adaptive manner. Some architectural design decisions (e.g., the provided memory interface, number of ports, and bit-width per port) have a strong impact on the efficiency, whereas other design decisions (e.g., how the reconfigurable fabric is used to implement application-specific accelerators)...
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