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This paper describes a high-speed CMOS transceiver that can run at a rate of up to 3.125Gbps, from a 1.8V power supply. The chip includes 10/20:1 full duplex Serializer/Deserializer, (SERDES), novel clock and data recovery circuits, and high-speed differential I/Os. Special techniques have been used to increase the jitter tolerance as well as to reduce the amount of output jitter. The chip has been...
A nonvolatile latch has been demonstrated using Giant-Magneto-Resistance (GMR) thin film resistors placed atop a conventional .35µm bulk CMOS process. The latch employs two GMR resistors that are programmed in complementary states by a pulse of 20- 50mA current passing through metal lines placed immediately below the resistors. Sensing of the relative resistor values is accomplished via a cross-coupled...
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