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Unlike classical floorplanning that usually only handles block packing to minimize silicon area, modern VLSI floorplanning typically needs to pack blocks within a fixed die(outline) with various user defined constraints. Many algorithms of floorplanning now are with fixed-outline constraint, and these algorithms handle this constraint in the process of stochastic iterative optimization. But the process...
As technology advances, the voltage (IR) drop in the power/ground (P/G) network becomes a serious problem in modern IC design. The P/G network co-design with floorplan can improve the power design quality. Different with traditional approaches which analyze P/G network during the floorplanning iterations, in this paper, an efficient pattern selection method is used to provide gradient information...
In current VLSI design, routing congestion becomes a critical issue with deep submicron design technology. In order to avoid the rip-up and reroute which is a time-consuming process after the placement stage, in this paper, we proposed a new two-stage floorplanning approach for congestion optimization. In our approach we use the method of probability-estimation which uses the extended bounding box...
In this paper, we present a floorplanning tool that aims at reducing hot spots and distributing temperature evenly cross a chip while optimizing the traditional design metric, chip area and total wire length. The floorplanning problem is represented by corner block list, and a tool called HotSpot is used to calculate floorplanning temperature based on the power dissipation, the physical dimension,...
In this paper, a floorplanner for low power designs is presented. The fuzzified technique and the simulated annealing algorithm are employed by targeting low power dissipation and high performance. Due to the imprecise nature of design information at the floorplanning stage, the various objectives are expressed in fuzzy domain. The search is made to a vector of fuzzy goals. The performance of the...
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