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Low cost through silicon via (TSV) technology is a key enabler for the future performance growth of various semiconductor devices. Deep etching and solder filling for TSV through pre-stacked silicon wafers make the TSV process much simpler. Polymer insulator also contributes to stress reduction and conformal insulation. In this paper, we investigate the barrier effect of polymer insulators on metal...
Mechanical strain/stress and crystal defects are produced in extremely thin wafers (thickness ~10 μm) of 3D-LSIs not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density microbumps and curing. Furthermore, the metal of through-Si via (TSV) and microbump not only becomes the cause of contamination, but also induces strain/stress (due to the difference in the co-efficient...
A novel stack joining process using newly designed pre-applied underfill for specifically 3D stacked chip was developed. The 3D chip stack process using this technique enables process time reduction and improvement of 3D device reliability because the multi stacked chip experiences only one soldering temperature cycle for joining.
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