The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets. A high performance NMOS achieves an fT of 420GHz. Concurrently, a low leakage 30pA/um NMOS achieves an fT of 218GHz. Deep-nwell/guard rings improves noise isolation by >50dB. High...
The power distribution network (PDN) analysis, including chip, quad-flat-package (QFP) and two-layer board, was presented for the cost-effective system design in the high-speed IO application. The physical interaction between the high-inductive shared off-chip design and capacitive on-chip network was discussed to figure out the related potential issues, such as anti-resonance and the serious interference...
A leading edge 32 nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match transistors, interconnects, RF/analog passive elements, embedded memory, and noise mitigation options. The low gate leakage of the high-k gate dielectric...
In this paper, the analysis of the power distribution system(PDS), including chip, package and board, was presented for system level design in the high-speed IO application. The integrated-analysis methodology was to link different scale physical geometries in an interactive platform. Instead of using the traditional time-domain simulation, the IO power distribution system characteristics were analyzed...
A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45 nm bulk CMOS technology has been achieved with measured fT/fMAX values...
In this paper, the analysis of the power distribution system(PDS), including chip, package and board, was presented for system level design in the high-speed IO application. The integrated-analysis methodology was to link different scale physical geometries in an interactive platform. Instead of using the traditional time-domain simulation, the IO power distribution system characteristics were analyzed...
An RF transceiver for operation near 24 GHz with an onchip antenna, fractional-N synthesizer and other RF and analog baseband circuits is demonstrated in 130-nm CMOS. A 5-m wireless link was demonstrated using a transceiver pair. A technique for wireless calibration of an on-chip frequency reference is also demonstrated.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.