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The simulation of fine-grained latency tolerance based on the dynamic state of the system in high-level simulation of many-core systems is a challenging simulation problem. We have introduced a high-level simulation technique for microthreaded many-core systems based on the assumption that the throughput of the program can always be one cycle per instruction as these systems have fine-grained latency...
High-level simulation is becoming commonly used for design space exploration of many-core systems. We have been working on high-level simulation techniques for the microthreaded many-core architecture at the University of Amsterdam. In previous work different levels of high-level simulation for instruction execution have been proposed, where the objective of every level is to keep the highest possible...
To harness the potential of CMPs for scalable, energy-efficient performance in general-purpose computers, the Apple-CORE project has co-designed a general machine model and concurrency control interface with dedicated hardware support for concurrency management across multiple cores. Its SVP interface combines dataflow synchronisation with imperative programming, towards the efficient use of parallelism...
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