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In 3DIC design, we may face the problem in manufacturing faults of through silicon vias (TSVs) and microbumps, and it will cause insufficient power delivery and eventually result in fatal error of functioning. In this work, we propose a power TSV/microbump fault tolerance scheme to resolve this issue. First, we use a fast heuristic to predict the worst IR-drop distribution under a given faulty rate...
Three-dimensional (3-D) integration using through-silicon-via (TSV) is an emerging technology for integrated circuit (IC) design. It has been used in DRAM die stacking extensively. However, yield remains a key issue for volume production of 3-D RAMs. In this paper, we present a point-to-point interconnection structure derived from bus and propose a fault tolerance interface scheme for TSVs and micro...
<?Pub Dtl?>Memory, especially DRAM, is one of the candidates to be considered in three-dimensional integrated circuit (3-D IC), and in particular, to be heterogeneously stacked with a system on chip (SOC) for mobile applications. Even though the memory is tested and repaired beforehand, the known good die (KGD) can become bad during the integration process. Traditional schemes may not be able...
3D ICs based on Through-Silicon-Vias (TSVs) enable the stacking of logic and memory dies to manufacture chips with higher performance, lower power, and smaller form factor. To improve the yield of the memory dies in 3D ICs, this paper proposes aBuilt-In Self-Repair (BISR) architecture which allows the sharing of spares between different layers of dies. The corresponding pre-bond (before the memory...
As we adopt more advanced process technologies, the volume production of memory devices, such as DRAM and Flash, becomes more difficult. It seems inevitable that during the ramp-up period, the initial manufacturing yield will be lower, and it takes more time and effort to improve the yield to a reasonable level. Although redundancy can be used to improve the yield eventually, the reserved spares may...
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