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This paper reports Super-Junction NLDMOS device implemented in Freescale's 0.13 μm SOI based Smart Power IC technology. This SJ device can be operated at both high and low side applications without back-gate effect. It achieves breakdown voltage of 111V and Rds.on × area of 138 mΩ.mm2 with robust characteristics.
Power device safe operating area (SOA), ESD immunity and energy capability are of particular importance for smart power IC technologies used in harsh applications. This paper discusses some of the powerful drain and body engineering techniques used in Freescale's advanced smart power technology to provide robust device characteristics.
This paper examines CMOS latchup immunity for a wide range of structures in a 0.25 mum smart power technology. The impact of logic ground isolation from the substrate and the presence of P+ and N+ buried layers below the logic wells is quantified
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