The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A modulated training pattern for intra-panel interface is proposed and is applied to design power-efficient clock and data recovery (CDR) circuits for intra-panel interface. By modulating the position of the rising edge of the training pattern, the number of the delay cells to generate the multi-phase clock to capture display data safely is reduced. As a result, power, area, and electro-magnetic interference...
In wafer-scale CMOS image sensors, the 3-transistor structure suffers from its low speed. To overcome this limitation, we propose a digital pixel sensor which has a digital-pixel output instead of analog-pixel output as in a conventional 3-transistor pixel. The digital pixel sensor can provide a high frame because it eliminates analog-to-digital conversion time. In addition, it removes the noise from...
This paper presents a high-voltage driver in nanometer-scale, low-voltage SOI CMOS technology well beyond the voltage limits of standard devices. The drive level is near the voltage-tolerance limit of the body insulator. A novel, bidirectional, switched-capacitor output stage that combines both voltage-conversion and pulse-drive is introduced. The two-level driver is implemented in 45-nm SOI CMOS...
A 60 GHz power amplifier (PA) using standard 90 nm CMOS technology is presented. This PA has power gain greater than 30 dB and 18.3 peak power added efficiency (PAE) under 2 V supply voltage. The parallel arrayed cascode power cells, which have a small number of fingers, are combined by the delay line to produce high gain and high PAE. Common gate inductors are inserted as gain booster circuits. A...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.