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The emergence of many-core processors raises novel demands to system design. Power-limitations and abundant parallelism require for efficient and scalable run-time management. The integration of dedicated hardware to enhance the performance of the run-time management system is gaining an increasing importance. But the design of a run-time manager for many-core generally suffers from exhaustive evaluation...
We present a comprehensive simulation environment for design space exploration in Asymmetric 3D-Networks-on-chip (A-3D-NoCs) covering the heterogeneity in 3D-System-on-chips (3D-SoCs). A challenging aspect of A-3D-NoC design is the consideration of interwoven parameters of the communication infrastructure and characteristics of the manufacturing technologies. Thus, simultaneous evaluation of multiple...
The increasing number of processing elements on embedded many-cores gives novel challenges for the chip design. Dedicated hardware has become an important feature to support the applied operating system and to improve the overall system efficiency. Since evaluation of novel architectures requires time expensive simulations or prototyping, transaction-level analysis gives an appropriate tool for early...
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