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We present a comprehensive simulation environment for design space exploration in Asymmetric 3D-Networks-on-chip (A-3D-NoCs) covering the heterogeneity in 3D-System-on-chips (3D-SoCs). A challenging aspect of A-3D-NoC design is the consideration of interwoven parameters of the communication infrastructure and characteristics of the manufacturing technologies. Thus, simultaneous evaluation of multiple...
Many-core systems provide abundant computing power for parallel applications. The run-time manager of an embedded system has to efficiently exploit the available resources while guaranteeing a high responsiveness. We propose a dedicated hardware infrastructure to improve the scalability and responsiveness of a run-time task manager. The hardware enhancements constitute a hierarchy of global and local...
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