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In recent years, various types of gas-fueled combined heat and power (CHP) systems have been developed and introduced into sites such as hospitals, hotels, commercial buildings, district heating & cooling centers, factories, etc., to increase energy savings and reduce greenhouse gases. Typical components integrated into CHP systems are gas engines (GE), gas turbines (GT), and fuel cells (FC);...
An analog-to-digital and time-to-digital converter using a common architecture (Time A/D converter TAD) is presented. Its resolutions for both analog-to-digital converter (ADC) mode and time-to-digital converter (TDC) mode are settable. The circuit structure is a completely digital circuit including a ring-shaped pulse-delay-line (RDL) driven by an input voltage Vin, along with an RDL synchronous...
An all-digital A/D converter TAD (time A/D converter) with 0.0027 mm2 is presented. The circuit structure is completely digital including a pulse-delay-line driven by Vin (input voltage), along with a counter, latch, and encoder. The TAD is easily shrinkable with the advancement in CMOS process technologies without any change of circuit architecture. Thanks to this construction, A/D conversion resolution...
A 0.18-mum CMOS RCC (radio-controlled clock) receiver IC with TAD (Time A/D converter) and ADPLL was realized. This IC, which receives low-frequency (LF) standard time waves, performs AM detection with digital circuits. It has two key components. First, TAD is an all-digital analog-to-digital converter, whose voltage resolution is settable (15 muV/LSB at 100 kS/s and 3.1 mV/LSB at 20 MS/s). Second,...
We report the fabrication of spot-size converters to efficiently connect a rib-type silicon wire waveguide with an optical fiber. The spot-size converter consists of a channel-type Si inverse taper core without a slab section and a SiOx waveguide that covers the taper. To make the Si taper core, we eliminate the Si slab at the end of the rib waveguide using a two-step etching process. The coupling...
An all-digital PLL that generates arbitrary output clock frequencies with only one reference clock frequency is presented. The method adopted in this study uses multiplying/dividing numbers with decimals. A ring-delay-line (RDL) consisting of 32 stages makes it possible for both the frequency detector and digitally-controlled oscillator to have a common time base, resulting in this unique clock generator...
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