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Now energy efficiency is becoming the most critical design facet for the scaling of Network-on-Chip (NoC). Different with electronic network, photonic Network-on-Chip offers natural solutions to reduce energy consumption. In this paper, we propose an energy-efficient photonic Network-on-Chip with central controller (CPNoC). Our proposed on-chip network utilizes a hybrid architecture, comprised of...
The demand of high-performance, scalable and energy-efficient on-chip interconnection network are growing in many-core processors. However, the limitations of the metallic interconnect make electronic Network-on-Chip inefficient. Photonic on-chip networks with advanced CMOS-compatible photonic devices, brings a bright future. In this paper, we present a hierarchical butterfly-based photonic Network-on-Chip,...
Future chip multiprocessors will requires low-power, high performance on-chip networks. Photonic interconnects is a promising way to leverage silicon photonics for future CMPs. In this paper, we present a highly scalable BPNoC(butterfly-based photonic NoC). The most important feature of our proposed network is that it can scale to a more large size with acceptable performance by utilizing the characteristics...
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