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Application mapping algorithm for reconfigurable architecture is one of the major research direction in reconfigurable computing. In this paper, we analyze the data memory bank conflict problem of the ACRPs (Application Customized Reconfigurable Pipelines) when exploiting the data parallelism and a conflict-free iteration-data mapping algorithm based on the operation mapping results is proposed to...
The parallelization of sequential programs and the optimization of critical loops are challenging issues in the time of multi-core architectures. Coarse-Grained Reconfigurable Architecture (CGRA) is introduced to accelerate these data-intensive applications, while the access delay introduced by the massive memory accesses contained in those loops has become the bottleneck of CGRA's performance. In...
With the on-chip resources largely increased, the computing paradigm of modern architectures are much different from traditional ones. The relation between temporal computing and spatial computing is getting more and more intricate. In this paper, a coarse-grained reconfigurable architecture is proposed named as programmable dataflow computing architecture: ProDFA. With both fine-grained control ability...
Domain specific design of reconfigurable architecture is a hard and time-consuming job. In this paper, a fast and effective domain-specific design method is proposed which mainly concludes a top-down subgraph enumeration algorithm and a heuristic identification process based on topological searching. A clustering and splitting algorithm is used to enumerate all the maximal valid subgraphs (MVSs) of...
The flexibility, performance and cost effectiveness of reconfigurable architectures have lead to its widespread use for embedded applications. Reconfigurable SoC (system-on-a-chip) design is very complex for multi-fields experts to collaborate on application algorithm design, hardware/software co-design and system decision. However, existing reconfigurable SoC design methods and environments can only...
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