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In this paper, we propose a novel asymmetrical 11T SRAM cell design that has fault correction capability. In addition, the Layout design through Error-Aware transistor Positioning (LEAP) technique is adopted in designing the layout of this proposed 11T cell. The area of the proposed 11T cell without using LEAP technique (regular 11T) is 76% larger than that of traditional 6T cell and 16% larger than...
Capacitance-voltage (C-V) and frequency dependent conductance-voltage (G-V) measurements have been carried out to investigate the charging and discharging effect induced by interface states and nanocrystalline Si (nc-Si) in floating gate MOS structures. Distinct conductance peaks are observed in the G-V curves for the floating gate with and without nc-Si dots. Based on the calculation of interface...
The nc-Si nonvolatile memory devices with high performance have been fabricated by using general CMOS techniques. High resolution transmission electronic microscope (HRTEM) shows that the average size of nc-Si is 8 nm and its density is 3×1011/cm2. The performance of programming/ erasing and retention time is mainly depending on the quality and thickness of tunnel layer and control layer. The results...
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