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The paper presents a unique design based on flash type ADCs having a high resolution. A novel cyclic architecture concept has been proposed for its implementation. The most important feature of this ADC is that two reference voltages are employed along with flash ADC logic. An 8 bit conventional flash type ADC requires 255 comparators for its implementation. Following this, a 4 bit flash type ADC...
A novel two-stage algorithm for constructing the orthogonal concavity tree (OCT) of a digital object is proposed. In Stage I, it derives the minimum-area orthogonal cover of the object. In Stage II, it constructs the orthogonal hull from the ortho-cover, and while doing so, extracts the orthogonal concavities in an iterative manner. Nested concavities, if any, are obtained by considering each concavity...
This paper presents Safe-ERfair, an efficient resource allocation strategy for handling overloads in real-time ERfair scheduled embedded systems. Each task has an assigned criticality value and consists of a mandatory part and an optional part. The scheduler employs an a priori look-ahead mechanism at the time of arrival of a new job to examine the occurrence of possible overloads during the execution...
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