The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A 10 Gb/s NRZ receiver with feedforward equalizer and CDR is described. The CDR incorporates an LC oscillator with a range of 8.3 to 11.1 GHz and a new glitch-free binary PFD. The glitch-free architecture minimizes the jitter generation of the CDR and increases jitter tolerance. The CDR loop employs a V/I converter with two independent charge-pumps for FD and PD signals to achieve fast acquisition...
A 10 Gb/s equalizer using both feedforward and decision-feedback equalization is designed for high speed serial-links. The chip is implemented in a standard 0.25 mum SiGe BiCMOS technology with 50 GHz peak ft, and packaged in a commercial LLP package. Using a 4-stage feedforward and 2-tap post-cursor cancellation, this equalizer achieves a total peak-to-peak jitter of 27 ps and 33 ps for 10"...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.