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In this paper, the crosstalk effects in future very large-scale integration (VLSI) interconnects based on multiwall carbon nanotubes (MWCNTs) are investigated with the equivalent single conductor (ESC) model and finite-difference time-domain (FDTD) solution of transmission line equations. The worst-case time delay and the peak crosstalk voltage on the victim wire of MWCNT interconnects are derived...
The minimum rectilinear Steiner tree (MRST) problem is an NP-hard problem, which is one of the fundamental issues in electronic design automation (EDA). Particle swarm optimization (PSO) has been proved to be an efficient intelligent algorithm for optimization designs. This paper presents an application of discrete particle swarm optimization (DPSO) for resolving MRST in VLSI routing and proposes...
As the continual decrease of the feature size, the parasitic inductance and capacitance effect play important role in IC design and verification. Previous works on layout extraction mainly concentrated on how to find out the type of devices and connections between them, few works has addressed the information of centerlines and widths of IC interconnects in a polygon-based VLSI layout, which are required...
In this paper, a modified Golumbic algorithm is presented to find the maximum set in a permutation graphs. The modified algorithm runs in O(n log n) times like the original algorithm[1], but some step timing O(n) in original algorithm is cut in the proposed method, then time consumption for solution is decreased by the modification. The example shows the anticipative result.
A fast inductance extraction engine is presented. With a fast multipole accelerated generalized minimal residual (GMRES) based three-dimensional (3-D) field solver, the software extracts parasitic inductance very quickly and accurately for interconnects with arbitrary geometries. The engine makes it possible the fast and highly-accurate analysis for critical nets in radio frequency (RF) application,...
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