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This paper shows a way to define a partially-exhaustive gate transition fault model for use in catching defects that escape when using more traditional fault models. We define the gate-level transitions ATPG must create for this fault model and how this may catch un-modeled defects. Future work will analyze results of applying tests generated using this fault model against a commercial chip design.
This paper describes a simple means to enable direct diagnosis by bypassing MISRs on a small set of tests while achieving ultimate output compression using MISRs for the majority of tests. By combining two compression schemes, XOR and MISRs in the same device, it becomes possible to have high compression and still support volume diagnostics.
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