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Trade-off between reliability and program time in 40nm TaOx-based Resistive random access memory (ReRAM) is experimentally investigated. By evaluating bit error rate (BER) and the current distributions, the complicated trade-off among Set/Reset cycles, reset voltage (VRESET) and with or without verify are investigated. At lower Set/Reset cycles, the current window is enhanced by introducing Set/Reset...
Error recovery effect of low resistance state (LRS) has been observed for the first time in set/reset cycling endurance in 40nm TaOx-based ReRAM cell. LRS error cells, which have an abnormally high resistance, are recovered to normal LRS by the relaxation time for error recovery between set and reset. This phenomenon can be explained by oxygen vacancy (VO) diffusion from TaOx layer to reconstruct...
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