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Smart Grid technologies are ever-increasingly being adopted by nations and governments, primarily for a huge technological advancement in the areas of power management and information and communications. The smart meters deployed in a household can monitor electricity usage in real-time, and aggregate the data for further analysis and control; however, the existing solutions mainly depend on Paillier's...
Filtering is a key component of many digital image/video processing algorithms. It often requires FIFO to temporarily buffer the pixels data for later usage. The FIFO size is proportional to the length of the filters and input data width, causing large area and power consumption. This paper presents a technique named FIFO with error-reduced data compression (FERDC) to reduce the FIFO size for various...
This paper presents an ASIC design of ultra-low power SAR ADC. To achieve ultra-low power, the proposed ADC operates at ultra-low voltage, deploying a single-ended structure and top plate sampling technique. In order to improve sampling circuit linearity at ultra-low supply voltage, a bootstrapped switch is developed. A non-binary redundant algorithm is applied to correct the inevitable decision errors...
Next-generation Wireless Body Sensor Networks (WBSNs) calls for miniaturization and power-efficient integration for long-term monitoring, real-time diagnostics and patient-centered healthcare solutions. However, state-of-the-art WBSN prototypes remain challenged by stringent power constraints and large form factors. The recently proposed asynchronous compressive sensing scheme suggests an efficient...
Sub-threshold operation has been proved to be successful to achieve minimum energy consumption. It is well known that the sub-threshold device sizing is different from super-threshold due to different current behavior. The previously reported sub-threshold sizing methods assume that the current is proportional to the transistor width. However, we have found that the inverse narrow width effect has...
We have investigated the impact of inverse narrow width effect on the threshold voltage and drain current in the near/sub-threshold region at three technology nodes (90 nm, 65 nm and 40 nm) and proposed a new sub-threshold device sizing method which is inverse-narrow-width-effect-aware to reduce the gate area, power consumption and delay. We applied the proposed sizing method in designing a 40 nm...
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